rev. prb october 2002 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a preliminary technical data adg3232* preliminary technical data one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 analog devices, inc., 2002 low voltage 2-1 mux level translator functional block diagram features operates from 1.65 v to 3.6 v supply rails uni-direction level translation, bidirectional signal path tiny 8 lead sot23 package short circuit protection* lvttl/cmos-compatible inputs applications level translation low voltage asic translation low voltage clock switching serial interface translation general description the adg3232 is a level translator 2-1 mux designed on a sub micron process which operates from supplies as low as 1.65 v. the device is guaranteed for operation over the supply range 1.65 v to 3.6 v. it operates from two supply voltages allowing bi-directional level translation, i.e. it translates low voltages to higher voltages and vice versa. the signal path is uni-directional, data may only flow from a to y. this type of device may be used in applications requiring communication between devices operating from different supply levels. the level translator mux is packaged in one of the smallest footprints available for its pin count. the 8 lead sot23 package requires only 8.26mm 2 board space. product highlights 1. uni-directional (up/down) level translation. 2. the device offers high performance and is fully guaranteed over a wide supply range; 1.65 v to 3.6 v. 3. short circuit protection* 4. tiny sot23 package. a1 gnd y v cc2 v cc1 a2 en *patent pending
?2? rev. prb adg3232?specifications 1 preliminary technical data parameter symbol c onditions min typ 2 max units logic inputs/outputs 3 input high voltage v ih v cc1 = 3.0 v to 3.6 v 1.35 v v cc1 = 2.3 v to 2.7 v 1.35 v v cc1 = 1.65 v to 1.95 v 0.65v cc v input low voltage v il v cc1 = 3.0 v to 3.6 v -0.5 0.8 v v cc1 = 2.3 v to 2.7 v -0.5 0.7 v v cc1 = 1.65 v to 1.95 v -0.5 0.35v cc v output high voltage v oh i oh = -100 a, v cc2 = 3.0 v to 3.6 v 2.4 v v cc2 = 2.3 v to 2.7 v 2.0 v v cc2 = 1.65 v to 1.95 v v cc - 0.45 v i oh = -4 ma, v cc2 = 2.3 v to 2.7 v 2.0 v v cc2 = 1.65 v to 1.95 v v cc - 0.45 v i oh = -8 ma, v cc2 = 3.0 v to 3.6 v 2.4 v output low voltage v ol i oh = 100 a, v cc2 = 3.0 v to 3.6 v -0.5 0.4 v v cc2 = 2.3 v to 2.7 v -0.5 0.4 v v cc2 = 1.65 v to 1.95 v -0.5 0.45 v i oh = 4 ma, v cc2 = 2.3 v to 2.7 v -0.5 0.4 v v cc2 = 1.65 v to 1.95 v -0.5 0.45 v i oh = 8 ma, v cc2 = 3.0 v to 3.6 v -0.5 0.4 v switchings characteristics 4,5 propagation delay, t pd a1 to y t phl, t plh 3.3 v 0.3 v, c l = 30 pf, v t = v cc /2 5 ns a2 to y t phl, t plh 3.3 v 0.3 v, c l = 30 pf, v t = v cc /2 5 ns a1 to y t phl, t plh 2.5 v 0.2 v, c l = 30 pf, v t = v cc /2 6 ns a2 to y t phl, t plh 2.5 v 0.2 v, c l = 30 pf, v t = v cc /2 6 ns a1 to y t phl, t plh 1.8 v 0.15 v, c l = 30 pf, v t = v cc /2 10 ns a2 to y t phl, t plh 1.8 v 0.15 v, c l = 30 pf, v t = v cc /2 10 ns enable time en to y t en 3.3 v 0.3 v, c l = 30 pf, v t = v cc /2 6 ns disable time en to y t dis 3.3 v 0.3 v, c l = 30 pf, v t = v cc /2 6 ns enable time en to y t en 2.5 v 0.2 v, c l = 30 pf, v t = v cc /2 8 ns disable time en to y t dis 2.5 v 0.2 v, c l = 30 pf, v t = v cc /2 7 ns enable time en to y t en 1.8 v 0.15 v, c l = 30 pf, v t = v cc /2 12 ns disable time en to y t dis 1.8 v 0.15 v, c l = 30 pf, v t = v cc /2 11 ns input leakage current i i 0 v in 3.6 v 1 a output leakage current i o 0 v in 3.6 v 1 a input capacitance 4 c in f = 1 mhz, v in = v cc or gnd 5 pf output capacitance 4 c o f = 1 mhz, v in = v cc or gnd 5 pf max data rate tbd mbps jitter tbd ps power requirements power supply voltages v cc1 1.65 3.6 v v cc2 1.65 3.6 v quiescent power supply current i cc1 digital inputs = 0 v or v cc 5a i cc2 digital inputs = 0 v or v cc 5a increase in i cc per input ? i cc12 v cc = + 3.6 v, one input at 3.0 v; others at v cc or gnd 100 a notes 1 temperature range is as follows: b version: ?40c to +85c. 2 all typical vlaues are at v cc1 = v cc2 , t a = +25c unless otherwise stated. 3 v il and v ih levels are specified with respect to v cc1 , while v oh and v ol levels are with respect to v cc2 . 3 guaranteed by design, not subject to production test. 4 see test circuits and waveforms. specifications subject to change without notice. (v cc1 = v cc2 = +1.65 v to 3.6 v, gnd = 0 v, all specifications t min to t max unless otherwise noted)
adg3232 ?3? rev. prb preliminary technical data absolute maximum ratings 1 (t a = 25c unless otherwise noted) v cc to gnd . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to +4.6 v dc input voltage . . . . . . . . . . . . . . . . . . . -0.5 v to +4.6 v dc output current . . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating temperature range industrial (b version) . . . . . . . . . . . . . . ?40c to +85c storage temperature range . . . . . . . . . ?65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . 150c 8 lead sot23, ja thermal impedance . . . . . . . . . . . . . . . . . . . . 211c/w lead temperature, soldering (10seconds) . . . . . . . 300c ir reflow, peak temperature (<20 seconds) . . . +235c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specication is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg3232 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model temperature range package description branding package option ADG3232BRJ ?40c to +85c sot23 w3b rj-8 pin configurations 8 lead sot23 package (rj-8) adg3232 (not to scale) vcc1 a1 a2 en 1 2 3 4 5 6 7 8 vcc2 nc y gnd warning! esd sensitive device
adg3232 ?4? rev. prb preliminary technical data typical performance characteristics tbd tpc 1. i cc vs. input signal frequency. tbd tpc 4. propagation delay vs temperature tbd tpc 2. v cc supply vs temperature tbd tpc 5. propagation delay vs split supply. tbd tpc 3. rise/fall time vs capacitive load tbd tpc 6. propagation delay vs capacitive load
adg3232 ?5? rev. prb preliminary technical data figure 1. propagation delay input 0v v oh v ol t plh t phl output v cc1 v t v t test circuits en t en y t dis v t 0v vol v oh v cc1 v t v t a1 0v v cc1 a2 0v v cc1 figure 2. enable & disable times signal input v cc1 device 1 signal output v cc2 device 2 a1 gnd y v cc2 v cc1 a2 en signal input device 1 v cc1 figure 3. typical operation circuit of the adg3233 description the adg3232 is a mux level translating device designed on a sub micron process which operates from supplies as low as 1.65 v. the device is guaranteed for operation over the supply range 1.65 v to 3.6 v. it operates from two supply voltages allowing uni-directional level translation. the adg3232 can translates low voltages to higher voltages and vice versa. a1 & en en en en en input the a1 and enable ( en ) inputs have v il /v ih logic levels so that it can accept logic levels of v ol /v oh from device 0 or the controlling device independent of the value of the supply being used by the controlling device. operation figure 3 shows the adg3232 in a typical application, the signal paths are from a1 or a2 to y. the device will level translate the signal applied to a1/a2 from a v cc1 logic level (this level translation can be either to a higher or lower supply) and route the signal to the y output, which will have standard v ol /v oh levels for v cc2 supplies. the supplies in figure 3 may be any combination of supplies, i.e. v cc0 , v cc1 and v cc2 may be any combination of supplies, for example: 1.8, 2.5, 3.3v.
?6? adg3232 rev. prb preliminary technical data outline dimensions dimensions shown in inches and (mm). 8 lead sot23 (rj-8) 1234 8765 0.118 (3.00) 0.110 (2.80) pin 1 0.077 (1.95) bsc 0.026 (0.65) bsc 0.069 (1.75) 0.059 (1.50) 0.008 (0.20) 0.004 (0.09) 0.022 (0.55) 0.014 (0.35) 10 0 0.015 (0.38) 0.009 (0.22) 0.006 (0.15) 0.000 (0.00) 0.051 (1.30) 0.035 (0.90) seating plane 0.057 (1.45) 0.035 (0.90) 0.118 (3.00) 0.102 (2.60)
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